Memory Address Translation

Memory Address Translation is a hardware–software mechanism in computer systems that maps virtual addresses generated by a processor to physical addresses in main memory, enabling efficient and protected memory access within the memory hierarchy.

87

Publications

4.1K

Citations

266

Authors

89

Institutions

Publications per year

2017–2026

24

Authors

266

  1. AB
    Abhishek Bhattacharjee

    Rutgers, The State University of New Jersey, United States

    6 publications · 322 citations

    6

    h-index

  2. JH
    Jaehyuk Huh

    Korea Advanced Institute of Science and Technology, South Korea

    4 publications · 76 citations

    4

    h-index

  3. CH
    Chang Hyun Park

    Korea Advanced Institute of Science and Technology, South Korea

    3 publications · 59 citations

    3

    h-index

  4. DJ
    Daniel J. Sorin

    Duke University, United States

    3 publications · 56 citations

    3

    h-index

  5. TK
    Tei‐Wei Kuo

    National Taiwan University, Taiwan

    3 publications · 180 citations

    3

    h-index

1–5 of 266

Venues

  1. IEEE Micro

    4 publications · 85 citations

    4

    h-index

  2. ACM SIGARCH Computer Architecture News

    3 publications · 59 citations

    3

    h-index

  3. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 2 publications · 53 citations

    2

    h-index

  4. IEEE Transactions on Computers

    2 publications · 54 citations

    2

    h-index

  5. IEEE Transactions on Consumer Electronics

    2 publications · 725 citations

    2

    h-index

1–5