Lut Placement

LUT Placement is a methodological contribution within the domain of digital circuit optimization that specifies the strategic assignment of Lookup Tables to particular physical or logical locations in a configurable architecture to enhance performance, reduce resource usage, or minimize routing complexity.

Publications

1.9K

Citations

132

Authors

Institutions

Publications per year

2017–2026

Parents

Lookup Tables

Publications

The effect of LUT and cluster size on deep-submicron FPGA performance and density

Elias Ahmed, Jonathan Rose · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 416 citations

Engineering, Computer Engineering, Computer Science +15

The CM-SAF operational scheme for the satellite based retrieval of solar surface irradiance — A LUT based eigenvector hybrid approach

Richard Mueller, C. Matsoukas, A. Gratzki et al. · Remote Sensing of Environment · 2009 · 273 citations

Natural Sciences, Earth Sciences, Meteorology +13

The effect of LUT and cluster size on deep-submicron FPGA performance and density

Elias Ahmed, Jonathan Rose · 2000 · 141 citations · Full text

Engineering, Computer Engineering, Computer Science +15

pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

João Dinis Ferreira, Gabriel Falcão, Juan Gómez-Luna et al. · 2022 · 53 citations

Engineering, Computer Engineering, Computer Science +16

The Implementation of Lua 5.0

Roberto Ierusalimschy, Luiz Henrique de Figueiredo · 2005 · 51 citations · Full text

Computing, Computer Engineering, Computer Science +14

1–5 of 48

Authors

132

AM
Alan Mishchenko
University of California, Berkeley, United States
3 publications · 80 citations
3
h-index
SJ
Stephen Jang
University of California, Berkeley, United States
3 publications · 80 citations
3
h-index
TN
T. Nandha Kumar
University of Nottingham Malaysia Campus, Malaysia
3 publications · 64 citations
3
h-index
JR
Jonathan Rose
University of Toronto, Canada
3 publications · 571 citations
3
h-index
BC
Billy Chan
University of California, Berkeley, United States
2 publications · 60 citations
2
h-index

1–5 of 132

Institutions

1–8 of 50

Venues

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2 publications · 456 citations
2
h-index
Calhoun: The Naval Postgraduate School Institutional Archive (Naval Postgraduate School)
Repository · 1 publications · 11 citations
1
h-index
Computers & Graphics
1 publications · 15 citations
1
h-index
AEU - International Journal of Electronics and Communications
1 publications · 12 citations
1
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 publications · 48 citations
1
h-index

1–5