LUT Packing is a synthesis optimization technique that belongs to the class of logic minimization methods, specifically distinguished by its coalescing of multiple lookup table operations into a single reconfigured lookup table to improve area and performance in FPGA-based circuit designs.
20
Publications
661
Citations
49
Authors
19
Institutions
Publications per year
2017–2026
2
Parents
Publications
20
Automatic Generation of Efficient Accelerators for Reconfigurable Hardware
David Koeplinger, Raghu Prabhakar, Yaqi Zhang et al. · 2016 · 69 citations · Full text
Elaheh Bozorgzadeh, Seda Ogrenci-Memik, Majid Sarrafzadeh · 2001 · 64 citations
1–5 of 20
Authors
49
- JH
5
h-index
- JL
3
h-index
- MS
3
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- CK
2
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- PD
2
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1–5 of 49
Institutions
19
University of Toronto
Toronto, Canada
5 h-index
12 publications
457 citations
University of California, Los Angeles
Los Angeles, United States
3 h-index
4 publications
151 citations
Xilinx (United States)
San Jose, United States
3 h-index
6 publications
134 citations
Northwestern University
Evanston, United States
3 h-index
3 publications
133 citations
Stanford University
Stanford, United States
2 h-index
12 publications
822 citations
University of California, Irvine
Irvine, United States
2 h-index
2 publications
76 citations
Cornell University
Ithaca, United States
2 h-index
2 publications
137 citations
University of Tehran
Tehran, Iran
1 h-index
3 publications
87 citations
1–8 of 19
Venues
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1 publications · 15 citations
1
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- Arabian Journal for Science and Engineering
1 publications · 13 citations
1
h-index
- ACM Transactions on Design Automation of Electronic Systems
TODAES · 1 publications · 20 citations
1
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 publications · 32 citations
1
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- ACM SIGARCH Computer Architecture News
1 publications · 68 citations
1
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1–5