Lut Interconnect Optimization
LUT Interconnect Optimization is a computational methodology within field-programmable gate array (FPGA) synthesis that specifically optimizes the routing and connectivity of Lookup Tables (LUTs) to minimize signal delay and resource utilization while maintaining logical equivalence.
13
Publications
460
Citations
35
Authors
12
Institutions
Publications per year
2017–2026
1
Parents
13
A fast carry chain adder for Virtex-5 FPGAs
Paolo Zicari, Stefania Perri · 2010 · 28 citations
Sayak Ray, A. Mishchenko, Niklas Eén et al. · 2012 · 28 citations
1–5 of 13
35
Indian Institute of Science Education and Research Kolkata, India
2 publications · 48 citations
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2
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2
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2
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1–5 of 35
12
University of California, Berkeley
Berkeley, United States
3 h-index
9 publications
351 citations

University of Ljubljana
Ljubljana, Slovenia
1 h-index
2 publications
138 citations

Clarkson University
Potsdam, United States
1 h-index
1 publications
12 citations

University of Calabria
Rende, Italy
1 h-index
2 publications
56 citations

Anna University, Chennai
Chennai, India
1 h-index
2 publications
42 citations
University of Virginia
Charlottesville, United States
1 h-index
2 publications
78 citations
Altera (United Kingdom)
High Wycombe, United Kingdom
1 h-index
2 publications
40 citations

Indian Institute of Technology Madras
Chennai, India
1 h-index
2 publications
42 citations
1–8 of 12
1 publications · 22 citations
1
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1 publications · 21 citations
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1 publications · 10 citations
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