Lut Interconnect Optimization

LUT Interconnect Optimization is a computational methodology within field-programmable gate array (FPGA) synthesis that specifically optimizes the routing and connectivity of Lookup Tables (LUTs) to minimize signal delay and resource utilization while maintaining logical equivalence.

13

Publications

460

Citations

35

Authors

12

Institutions

Publications per year

2017–2026

1

Authors

35

  1. SR
    Sayak Ray

    Indian Institute of Science Education and Research Kolkata, India

    2 publications · 48 citations

    2

    h-index

  2. CC
    Chao Chen

    Institute of Science and Technology Austria, Austria

    2 publications · 48 citations

    2

    h-index

  3. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    2 publications · 48 citations

    2

    h-index

  4. NE
    Niklas Eén

    University of California, Berkeley, United States

    2 publications · 48 citations

    2

    h-index

  5. SK
    Sinan Kaptanoglu

    Bio-Technical Resources (United States), United States

    2 publications · 38 citations

    2

    h-index

1–5 of 35

Venues

  1. 1

    h-index

  2. Annals of Telecommunications

    1 publications · 21 citations

    1

    h-index

1–3