Low-latency Interface Design
Low-Latency Interface Design is a methodological framework within interface protocol implementation that minimizes signal processing and data transmission delays to enable real-time or near-real-time communication between interconnected systems, distinguished by its focus on optimizing timing performance and reducing architectural bottlenecks in hardware-software interfaces.
46
Publications
1.9K
Citations
172
Authors
50
Institutions
Publications per year
2017–2026
7
46
The Virtual Interface Architecture
Dave Dunning, G. Regnier, G. McAlpine et al. · IEEE Micro · 1998 · 291 citations
Arsenic: a user-accessible gigabit Ethernet interface
Ian Pratt, Keir Fraser · 2002 · 105 citations
A low-latency FIFO for mixed-clock systems
Tiberiu Chelcea, Steven M. Nowick · 2002 · 87 citations
Engineering, Computer Engineering, Electrical Engineering +15
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Columbia University
New York, United States
4 h-index
8 publications
790 citations

Cornell University
Ithaca, United States
3 h-index
8 publications
188 citations
Intel (United States)
Santa Clara, United States
3 h-index
16 publications
2.7K citations
Istituto Nazionale di Fisica Nucleare, Sezione di Pisa
Pisa, Italy
2 h-index
1 publications
27 citations
Stanford University
Stanford, United States
2 h-index
5 publications
163 citations
The Ohio State University
Columbus, United States
2 h-index
5 publications
103 citations
University of Monastir
Monastir, Tunisia
2 h-index
10 publications
125 citations
Istituto Nazionale di Fisica Nucleare, Sezione di Roma I
Rome, Italy
2 h-index
4 publications
108 citations
1–8 of 50
3 publications · 362 citations
3
h-index
2 publications · 164 citations
2
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JINST · 1 publications · 21 citations
2
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1 publications · 50 citations
1
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1 publications · 20 citations
1
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1–5