Latency Hiding Techniques

Latency Hiding Techniques is a computational optimization strategy in parallel computing that belongs to the class of performance-enhancement methods by overlapping computation or communication operations to mask the effects of memory or synchronization delays rather than reducing them.

90

Publications

4.7K

Citations

272

Authors

92

Institutions

Publications per year

2017–2026

13

Authors

272

  1. TC
    Todd C. Mowry

    Carnegie Mellon University, United States

    4 publications · 363 citations

    4

    h-index

  2. AN
    Akira Nukada

    Tokyo Institute of Technology, Japan

    3 publications · 65 citations

    3

    h-index

  3. XS
    Xian‐He Sun

    Illinois Institute of Technology, United States

    3 publications · 100 citations

    3

    h-index

  4. BH
    Bei Hua

    University of Science and Technology of China, China

    3 publications · 54 citations

    3

    h-index

  5. CC
    Chen-Yong Cher

    IBM Research - Thomas J. Watson Research Center, United States

    3 publications · 101 citations

    3

    h-index

1–5 of 272

Venues

  1. ACM SIGARCH Computer Architecture News

    2 publications · 66 citations

    2

    h-index

  2. ACM Transactions on Embedded Computing Systems

    TECS · 2 publications · 28 citations

    2

    h-index

  3. arXiv (Cornell University)

    Repository · 2 publications · 160 citations

    2

    h-index

  4. IEEE Transactions on Computers

    1 publications · 25 citations

    1

    h-index

  5. EPJ Web of Conferences

    1 publications · 13 citations

    1

    h-index

1–5