Interrupt Latency Optimization is a methodological approach in embedded systems engineering that minimizes the time interval between the occurrence of a hardware interrupt and the initiation of the corresponding interrupt service routine execution, thereby enhancing the system's real-time responsiveness and determinism.
21
Publications
363
Citations
70
Authors
24
Institutions
Publications per year
2017–2026
1
Parents
Publications
21
Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts
A Comprehensive Implementation and Evaluation of Direct Interrupt Delivery
Cheng-Chun Tu, Michael Ferdman, Chao-tung Lee et al. · 2015 · 32 citations
1–5 of 21
Authors
70
- ML
2
h-index
- DR
2
h-index
- CL
2
h-index
- CT
2
h-index
- PE
2
h-index
1–5 of 70
Institutions
24
Universität Hamburg
Hamburg, Germany
2 h-index
3 publications
48 citations
Oracle (United States)
Austin, United States
2 h-index
2 publications
44 citations
Stony Brook University
Stony Brook, United States
2 h-index
2 publications
44 citations
Technical University of Munich
Munich, Germany
2 h-index
12 publications
204 citations
Hong Kong Polytechnic University
Hong Kong, Hong Kong
2 h-index
6 publications
194 citations
Industrial Technology Research Institute
Hsinchu, Taiwan
2 h-index
4 publications
88 citations
Beihang University
Beijing, China
2 h-index
4 publications
171 citations
Humboldt-Universität zu Berlin
Berlin, Germany
1 h-index
1 publications
15 citations
1–8 of 24
Venues
- IEEE Transactions on Computers
1 publications · 24 citations
1
h-index
- IEEE Parallel & Distributed Technology Systems & Applications
1 publications · 22 citations
1
h-index
- International Symposium on Performance Evaluation of Computer and Telecommunication Systems
Conference · 1 publications · 14 citations
1
h-index
- ACM SIGPLAN Notices
1 publications · 12 citations
1
h-index
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1 publications · 22 citations
1–5