Instruction Set Emulation

Instruction Set Emulation is a computational preservation method that simulates the behavior of a target processor’s instruction set architecture in software, enabling the execution of legacy machine code on modern hardware by replicating the original processor’s operational semantics.

15

Publications

1.6K

Citations

36

Authors

14

Institutions

Publications per year

2017–2026

2

Authors

36

  1. DD
    Dino Dai Zovi

    University of New Mexico, United States

    2 publications · 409 citations

    2

    h-index

  2. TP
    Trek Palmer

    University of New Mexico, United States

    2 publications · 409 citations

    2

    h-index

  3. DS
    Darko Stefanović

    University of Novi Sad, Serbia

    2 publications · 409 citations

    2

    h-index

  4. EG
    Emilio G. Cota

    Columbia University, United States

    2 publications · 37 citations

    2

    h-index

  5. BC
    Bob Cmelik

    University of Washington, United States

    2 publications · 756 citations

    2

    h-index

1–5 of 36

Venues

  1. ACM SIGMETRICS Performance Evaluation Review

    PER · 1 publications · 114 citations

    1

    h-index

  2. Digital technical journal

    1 publications · 125 citations

    1

    h-index

  3. 1

    h-index

1–3