Instruction Fetch Unit
The Instruction Fetch Unit is a processor core component responsible for retrieving executable instructions from memory in accordance with the program counter, distinguishing itself from other fetch mechanisms by directly initiating the instruction pipeline in a pipelined microarchitecture.
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5.5K
Citations
371
Authors
96
Institutions
Publications per year
2017–2026
6
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132
Balancing thoughput and fairness in SMT processors
Kun Luo, Jayanth Gummaraju, M. Franklin · 2005 · 247 citations
Optimizing Compiler for the CELL Processor
Alexandre E. Eichenbergert, Kathryn O’Brien, Kevin O’Brien et al. · 2005 · 173 citations
Optimization of instruction fetch mechanisms for high issue rates
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills et al. · 1995 · 169 citations · Full text
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Institut de Recherche en Informatique et Systèmes Aléatoires, France
4 publications · 304 citations
4
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1–5 of 371
96
University of Michigan
Ann Arbor, United States
14 h-index
42 publications
2.2K citations
Carnegie Mellon University
Pittsburgh, United States
7 h-index
15 publications
444 citations
Intel (United States)
Santa Clara, United States
7 h-index
8 publications
473 citations
Universitat Politècnica de Catalunya
Barcelona, Spain
6 h-index
18 publications
684 citations
University of California San Diego
San Diego, United States
6 h-index
12 publications
502 citations
University of Illinois Urbana-Champaign
Urbana, United States
6 h-index
20 publications
557 citations
Institut national de recherche en sciences et technologies du numérique
Le Chesnay-Rocquencourt, France
5 h-index
7 publications
431 citations
Institut de Recherche en Informatique et Systèmes Aléatoires
Rennes, France
5 h-index
7 publications
431 citations
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8 publications · 269 citations
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4 publications · 238 citations
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2 publications · 97 citations
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1 publications · 24 citations
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