Instruction Fetch Unit

The Instruction Fetch Unit is a processor core component responsible for retrieving executable instructions from memory in accordance with the program counter, distinguishing itself from other fetch mechanisms by directly initiating the instruction pipeline in a pipelined microarchitecture.

132

Publications

5.5K

Citations

371

Authors

96

Institutions

Publications per year

2017–2026

6

Authors

371

  1. YN
    Yale N. Patt

    The University of Texas at Austin, United States

    9 publications · 473 citations

    9

    h-index

  2. TM
    Thomas M. Conte

    North Carolina State University, United States

    9 publications · 403 citations

    9

    h-index

  3. BC
    Brad Calder

    University of California San Diego, United States

    6 publications · 332 citations

    6

    h-index

  4. TY
    Tse-Yu Yeh

    University of Michigan, United States

    5 publications · 352 citations

    5

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  5. AS
    André Seznec

    Institut de Recherche en Informatique et Systèmes Aléatoires, France

    4 publications · 304 citations

    4

    h-index

1–5 of 371

Venues

  1. ACM SIGARCH Computer Architecture News

    8 publications · 269 citations

    8

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  2. IBM Journal of Research and Development

    4 publications · 238 citations

    4

    h-index

  3. IEEE Transactions on Computers

    3 publications · 165 citations

    3

    h-index

  4. 2

    h-index

  5. Computer

    1 publications · 24 citations

    1

    h-index

1–5