Hierarchical Verification is a formal method in systems engineering and design that systematically validates the correctness and consistency of components at multiple levels of a hierarchical decomposition, ensuring that lower-level specifications conform to their higher-level abstractions.
84
Publications
2.9K
Citations
192
Authors
99
Institutions
Publications per year
2017–2026
9
Parents
Publications
84
The structure of “THE”-multiprogramming system
Edsger W. Dijkstra · Communications of the ACM · 1983 · 177 citations · Full text
Stepwise refinement and verification in box-structured systems
Harlan D. Mills · Computer · 1988 · 137 citations
1–5 of 84
Authors
192
- RD
4
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- YL
3
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- RE
3
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- RA
3
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- MY
3
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1–5 of 192
Institutions
99
Carnegie Mellon University
Pittsburgh, United States
7 h-index
12 publications
378 citations
University of Pennsylvania
Philadelphia, United States
4 h-index
5 publications
288 citations
Nokia (United States)
Coppell, United States
4 h-index
5 publications
193 citations
Intel (United States)
Santa Clara, United States
4 h-index
4 publications
66 citations
University of Toronto
Toronto, Canada
4 h-index
10 publications
364 citations
SRI International
Menlo Park, United States
3 h-index
7 publications
507 citations
Menlo School
Atherton, United States
3 h-index
6 publications
423 citations
Bell (Canada)
Montreal, Canada
2 h-index
2 publications
104 citations
1–8 of 99
Venues
- Design Automation Conference
Conference · 5 publications · 223 citations
5
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- IEEE Transactions on Computers
4 publications · 187 citations
4
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- Communications of the ACM
3 publications · 327 citations
3
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- Research Showcase @ Carnegie Mellon University (Carnegie Mellon University)
Repository · 2 publications · 69 citations
2
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- International Conference on Computer Aided Design
Conference · 2 publications · 96 citations
2
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