Hazard Reduction
Hazard Reduction is a design methodology in digital integrated circuits that minimizes unintended transient behaviors in logic circuits during signal transitions, thereby reducing the risk of erroneous outputs and contributing to waste minimization through improved circuit reliability and energy efficiency.
134
Publications
5.9K
Citations
475
Authors
219
Institutions
Publications per year
2017–2026
39
134
Earthquake prediction - a statistician's view.
D. Vere‐Jones · Journal of Physics of the Earth · 1978 · 186 citations · Full text
Business, Insurance, Risk Management +17
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The University of Sydney
Sydney, Australia
4 h-index
10 publications
569 citations
University of Washington
Seattle, United States
4 h-index
7 publications
445 citations
Natural Hazards Research Australia
East Melbourne, Australia
3 h-index
12 publications
1.1K citations
Massachusetts Institute of Technology
Cambridge, United States
3 h-index
7 publications
401 citations

Pennsylvania State University
State College, United States
3 h-index
6 publications
152 citations

University of Amsterdam
Amsterdam, The Netherlands
3 h-index
3 publications
315 citations
Virginia Tech
Blacksburg, United States
3 h-index
5 publications
150 citations
United States Geological Survey
Reston, United States
3 h-index
5 publications
490 citations
1–8 of 219
4 publications · 259 citations
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3 publications · 154 citations
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3 publications · 349 citations
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3 publications · 132 citations
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3 publications · 232 citations
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