Hazard Reduction

Hazard Reduction is a design methodology in digital integrated circuits that minimizes unintended transient behaviors in logic circuits during signal transitions, thereby reducing the risk of erroneous outputs and contributing to waste minimization through improved circuit reliability and energy efficiency.

134

Publications

5.9K

Citations

475

Authors

219

Institutions

Publications per year

2017–2026

39

Authors

475

  1. LR
    L. Reijnders

    University of Amsterdam, Netherlands

    3 publications · 315 citations

    3

    h-index

  2. JB
    J.G. Bredeson

    Pennsylvania State University, United States

    2 publications · 60 citations

    2

    h-index

  3. PJ
    Peter J. Daugherty

    Pacific Northwest Research Station, United States

    2 publications · 78 citations

    2

    h-index

  4. SU
    S.H. Unger

    Columbia University, United States

    2 publications · 97 citations

    2

    h-index

  5. MP
    Malcolm Possell

    The University of Sydney, Australia

    2 publications · 35 citations

    2

    h-index

1–5 of 475

Venues

  1. Forest Ecology and Management

    4 publications · 259 citations

    4

    h-index

  2. Journal of Forestry

    3 publications · 154 citations

    3

    h-index

  3. Journal of Cleaner Production

    3 publications · 349 citations

    3

    h-index

  4. Nature Communications

    3 publications · 132 citations

    3

    h-index

  5. Journal of Hazardous Materials

    3 publications · 232 citations

    3

    h-index

1–5