Hardware-efficient Pruning

Hardware-Efficient Pruning is a model compression technique that systematically reduces neural network redundancy by removing less critical parameters or structures in a manner specifically optimized to enhance computational efficiency, reduce memory footprint, and accelerate inference on targeted hardware platforms.

104

Publications

5.8K

Citations

450

Authors

146

Institutions

Publications per year

2017–2026

97

Authors

450

  1. YW
    Yanzhi Wang

    Northeastern University, United States

    12 publications · 808 citations

    11

    h-index

  2. XL
    Xue Lin

    Northeastern University, United States

    8 publications · 497 citations

    8

    h-index

  3. ZL
    Zhengang Li

    Universidad del Noreste, Mexico

    7 publications · 319 citations

    7

    h-index

  4. WN
    Wei Niu

    William & Mary, United States

    6 publications · 315 citations

    6

    h-index

  5. XM
    Xiaolong Ma

    Northeastern University, United States

    5 publications · 347 citations

    5

    h-index

1–5 of 450

Venues

  1. arXiv (Cornell University)

    Repository · 17 publications · 826 citations

    13

    h-index

  2. IEEE Access

    5 publications · 112 citations

    5

    h-index

  3. 3

    h-index

  4. 3

    h-index

  5. 3

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1–5