Hardware-efficient Pruning
Hardware-Efficient Pruning is a model compression technique that systematically reduces neural network redundancy by removing less critical parameters or structures in a manner specifically optimized to enhance computational efficiency, reduce memory footprint, and accelerate inference on targeted hardware platforms.
104
Publications
5.8K
Citations
450
Authors
146
Institutions
Publications per year
2017–2026
97
Parents
104
Jiecao Yu, Andrew Lukefahr, David J. Palframan et al. · 2017 · 294 citations · Full text
Exploring the Regularity of Sparse Structure in Convolutional Neural Networks
Huizi Mao, Song Han, Jeff Pool et al. · arXiv (Cornell University) · 2017 · 230 citations · Full text
Shuo Wang, Zhe Li, Caiwen Ding et al. · 2018 · 226 citations · Full text
1–5 of 104
450
11
h-index
8
h-index
7
h-index
6
h-index
5
h-index
1–5 of 450
146
Tsinghua University
Beijing, China
11 h-index
34 publications
1.6K citations
Universidad del Noreste
Tampico, Mexico
8 h-index
35 publications
2.4K citations
William & Mary
Williamsburg, United States
5 h-index
10 publications
966 citations
University of Michigan
Ann Arbor, United States
4 h-index
15 publications
1.9K citations
University of Science and Technology of China
Hefei, China
4 h-index
10 publications
799 citations

Chinese Academy of Sciences
Beijing, China
4 h-index
29 publications
721 citations
Institute of Computing Technology
Beijing, China
4 h-index
28 publications
2K citations
University of Chinese Academy of Sciences
Beijing, China
4 h-index
17 publications
467 citations
1–8 of 146
Repository · 17 publications · 826 citations
13
h-index
5 publications · 112 citations
5
h-index
3 publications · 85 citations
3
h-index
3 publications · 152 citations
3
h-index
JETCAS · 3 publications · 116 citations
3
h-index
1–5