Hardware Trojan Modeling

Hardware Trojan Modeling is a methodological framework that formally characterizes the insertion, behavior, and detection of malicious modifications in integrated circuits to enable systematic analysis and evaluation of hardware security vulnerabilities.

42

Publications

3K

Citations

136

Authors

62

Institutions

Publications per year

2017–2026

20

Authors

136

  1. SB
    Swarup Bhunia

    Case Western Reserve University, United States

    4 publications · 997 citations

    4

    h-index

  2. YM
    Yiorgos Makris

    The University of Texas at Dallas, United States

    3 publications · 778 citations

    3

    h-index

  3. JP
    Jim Plusquellic

    University of New Mexico, United States

    2 publications · 195 citations

    2

    h-index

  4. MX
    Mingfu Xue

    Nanjing University of Aeronautics and Astronautics, China

    2 publications · 119 citations

    2

    h-index

  5. ZZ
    Ziqi Zhou

    Auburn University, United States

    2 publications · 98 citations

    2

    h-index

1–5 of 136

Venues

  1. 3

    h-index

  2. Integration

    2 publications · 35 citations

    2

    h-index

  3. IET Computers & Digital Techniques

    2 publications · 119 citations

    2

    h-index

  4. 2

    h-index

  5. IEEE Transactions on Dependable and Secure Computing

    TDSC · 1 publications · 20 citations

    1

    h-index

1–5