Hardware Trojan Modeling
Hardware Trojan Modeling is a methodological framework that formally characterizes the insertion, behavior, and detection of malicious modifications in integrated circuits to enable systematic analysis and evaluation of hardware security vulnerabilities.
42
Publications
3K
Citations
136
Authors
62
Institutions
Publications per year
2017–2026
20
Parents
42
Hardware Trojan detection using path delay fingerprint
Yier Jin, Yiorgos Makris · 2008 · 632 citations
Kun Xiao, Domenic Forte, Yier Jin et al. · ACM Transactions on Design Automation of Electronic Systems · 2016 · 455 citations · Full text
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University of Florida
Gainesville, United States
5 h-index
10 publications
1.7K citations
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
Paris, France
3 h-index
7 publications
268 citations
University of California, Santa Barbara
Santa Barbara, United States
3 h-index
12 publications
429 citations
Beijing Electronic Science and Technology Institute
Beijing, China
2 h-index
11 publications
203 citations
Auburn University
Auburn, United States
2 h-index
6 publications
294 citations
Case Western Reserve University
Cleveland, United States
2 h-index
6 publications
1.6K citations
Institute of Computing Technology
Beijing, China
2 h-index
3 publications
95 citations
University of Connecticut
Storrs, United States
2 h-index
2 publications
614 citations
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3 publications · 85 citations
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2 publications · 35 citations
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2 publications · 119 citations
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2 publications · 190 citations
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TDSC · 1 publications · 20 citations
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