Hardware Co-verification

Hardware Co-Verification is a verification methodology that integrates hardware and software components within a unified testbench environment to simultaneously validate the functional correctness and timing behavior of hardware designs against their software counterparts through joint simulation or emulation.

53

Publications

1.5K

Citations

208

Authors

78

Institutions

Publications per year

2017–2026

11

Variants

Hardware-software Co-verification

Authors

208

  1. FX
    Fei Xie

    Portland State University, United States

    4 publications · 93 citations

    4

    h-index

  2. BT
    Bassam Tabbara

    University of California, Berkeley, United States

    2 publications · 43 citations

    2

    h-index

  3. DB
    D. Becker

    Duke University, United States

    2 publications · 147 citations

    2

    h-index

  4. SG
    Sabine Glesner

    Technische Universität Berlin, Germany

    2 publications · 49 citations

    2

    h-index

  5. PH
    Paula Herber

    Technische Universität Berlin, Germany

    2 publications · 49 citations

    2

    h-index

1–5 of 208

Venues

  1. IBM Journal of Research and Development

    2 publications · 29 citations

    2

    h-index

  2. ACM Transactions on Embedded Computing Systems

    TECS · 2 publications · 44 citations

    2

    h-index

  3. 1

    h-index

  4. Electronics

    1 publications · 21 citations

    1

    h-index

  5. Journal of Information Processing Systems

    1 publications · 10 citations

    1

    h-index

1–5