Hardware Co-verification
Hardware Co-Verification is a verification methodology that integrates hardware and software components within a unified testbench environment to simultaneously validate the functional correctness and timing behavior of hardware designs against their software counterparts through joint simulation or emulation.
53
Publications
1.5K
Citations
208
Authors
78
Institutions
Publications per year
2017–2026
11
Variants
Hardware-software Co-verification
Parents
53
Methodology for hardware/software co-verification in C/C++
Luc Séméria, Abhijit Ghosh · 2002 · 116 citations
ArchC: A SystemC-Based Architecture Description Language
Sandro Rigo, Guido Araújo, Marcus Bartholomeu et al. · 2004 · 98 citations
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78
University of California, Berkeley
Berkeley, United States
4 h-index
8 publications
202 citations

Portland State University
Portland, United States
4 h-index
9 publications
211 citations
Intel (United States)
Santa Clara, United States
3 h-index
3 publications
149 citations
University of Kaiserslautern
Kaiserslautern, Germany
2 h-index
5 publications
118 citations
Technische Universität Berlin
Berlin, Germany
2 h-index
4 publications
85 citations
Synopsys (Switzerland)
Zurich, Switzerland
2 h-index
2 publications
198 citations
University of Oxford
Oxford, United Kingdom
2 h-index
7 publications
247 citations
Conexant (United States)
Irvine, United States
2 h-index
4 publications
84 citations
1–8 of 78
2 publications · 29 citations
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TECS · 2 publications · 44 citations
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Conference · 1 publications · 34 citations
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1 publications · 21 citations
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1 publications · 10 citations
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