Hardware Acceleration Interfaces

Hardware Acceleration Interfaces is a singular abstraction representing the standardized communication layer that enables interoperability between reconfigurable hardware accelerators and host systems by defining protocols, data formats, and control mechanisms for task offloading, synchronization, and resource management.

36

Publications

1.2K

Citations

138

Authors

39

Institutions

Publications per year

2017–2026

10

Authors

138

  1. RK
    Ryan Kastner

    University of California San Diego, United States

    3 publications · 229 citations

    3

    h-index

  2. MJ
    Matthew Jacobsen

    University of California San Diego, United States

    3 publications · 229 citations

    3

    h-index

  3. BB
    B. Blaner

    IBM (United States), United States

    2 publications · 212 citations

    2

    h-index

  4. JL
    Jing-Wun Lin

    National Cheng Kung University, Taiwan

    2 publications · 29 citations

    2

    h-index

  5. CC
    Chung‐Ho Chen

    Southern Taiwan University of Science and Technology, Taiwan

    2 publications · 29 citations

    2

    h-index

1–5 of 138

Venues

  1. IBM Journal of Research and Development

    2 publications · 212 citations

    2

    h-index

  2. 1

    h-index

  3. IEEE Computer Graphics and Applications

    1 publications · 10 citations

    1

    h-index

  4. International Workshop on OpenCL

    Conference · 1 publications · 22 citations

    1

    h-index

  5. IEEE Micro

    1 publications · 37 citations

    1

    h-index

1–5