Hardware Acceleration Interfaces
Hardware Acceleration Interfaces is a singular abstraction representing the standardized communication layer that enables interoperability between reconfigurable hardware accelerators and host systems by defining protocols, data formats, and control mechanisms for task offloading, synchronization, and resource management.
36
Publications
1.2K
Citations
138
Authors
39
Institutions
Publications per year
2017–2026
10
Parents
36
CAPI: A Coherent Accelerator Processor Interface
Jeffrey Stuecheli, B. Blaner, C. Johns et al. · IBM Journal of Research and Development · 2015 · 166 citations
Matthew Jacobsen, Dustin Richmond, Matthew Hogains et al. · ACM Transactions on Reconfigurable Technology and Systems · 2015 · 133 citations
The Tyzx DeepSea G2 Vision System, ATaskable, Embedded Stereo Camera
J. Woodfill, G. Gordon, Dave Jurasek et al. · 2006 · 59 citations
1–5 of 36
138
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Southern Taiwan University of Science and Technology, Taiwan
2 publications · 29 citations
2
h-index
1–5 of 138
39
University of California San Diego
San Diego, United States
3 h-index
9 publications
765 citations
Xilinx (United States)
San Jose, United States
2 h-index
4 publications
54 citations

Delft University of Technology
Delft, The Netherlands
2 h-index
8 publications
147 citations
National Cheng Kung University
Tainan City, Taiwan
2 h-index
9 publications
127 citations
Humboldt-Universität zu Berlin
Berlin, Germany
1 h-index
1 publications
15 citations
University of California System
Oakland, United States
1 h-index
2 publications
70 citations

Democritus University of Thrace
Komotini, Greece
1 h-index
4 publications
60 citations
University of California, Davis
Davis, United States
1 h-index
2 publications
36 citations
1–8 of 39
2 publications · 212 citations
2
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1 publications · 133 citations
1
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1 publications · 10 citations
1
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Conference · 1 publications · 22 citations
1
h-index
1 publications · 37 citations
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1–5