Floorplanning for Partial Reconfiguration is a design methodology in field-programmable gate array (FPGA) systems engineering that allocates and constrains reconfigurable modules to specific physical regions on the programmable fabric to ensure spatial and temporal isolation while enabling dynamic hardware reconfiguration.
12
Publications
386
Citations
37
Authors
17
Institutions
Publications per year
2017–2026
0
Parents
Publications
12
Go Ahead: A Partial Reconfiguration Framework
Christian Beckhoff, Dirk Koch, Jim Tørresen · 2012 · 123 citations
1–5 of 12
Authors
37
- MD
3
h-index
- JT
2
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- DK
2
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- CB
2
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- MR
2
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1–5 of 37
Institutions
17
Politecnico di Milano
Milan, Italy
3 h-index
9 publications
227 citations
University of Illinois Chicago
Chicago, United States
2 h-index
2 publications
61 citations
University of Oslo
Oslo, Norway
2 h-index
6 publications
435 citations
Institut National Polytechnique de Toulouse
Toulouse, France
1 h-index
2 publications
22 citations
Technical University of Munich
Munich, Germany
1 h-index
2 publications
44 citations
Luna Innovations (United States)
Roanoke, United States
1 h-index
1 publications
14 citations
Nvidia (United Kingdom)
Reading, United Kingdom
1 h-index
1 publications
43 citations
Technische Universität Dresden
Dresden, Germany
1 h-index
1 publications
19 citations
1–8 of 17
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 publications · 43 citations
1
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- IEEE Personal Communications
1 publications · 23 citations
1
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1 publications · 36 citations
1
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- Canadian Journal of Electrical and Computer Engineering
1 publications · 10 citations
1–4