Fence Instructions

Fence Instructions is a synchronization mechanism in memory consistency models that enforces a global ordering constraint on memory operations by ensuring that all memory accesses before the fence are globally visible before any memory accesses after the fence.

22

Publications

944

Citations

63

Authors

25

Institutions

Publications per year

2017–2026

5

Authors

63

  1. MV
    Martin Vechev

    ETH Zurich, Switzerland

    3 publications · 132 citations

    3

    h-index

  2. EY
    Eran Yahav

    Technion – Israel Institute of Technology, Israel

    3 publications · 132 citations

    3

    h-index

  3. NN
    Nayden Nedev

    Princeton University, United States

    2 publications · 93 citations

    2

    h-index

  4. EK
    Elliot K. Kolodner

    IBM Research - Haifa, Israel

    2 publications · 114 citations

    2

    h-index

  5. CL
    Changhui Lin

    University of California, Riverside, United States

    2 publications · 25 citations

    2

    h-index

1–5 of 63

Venues

  1. ACM SIGPLAN Notices

    2 publications · 36 citations

    2

    h-index

  2. IEEE Transactions on Computers

    1 publications · 78 citations

    1

    h-index

  3. 1

    h-index

  4. ACM SIGACT News

    1 publications · 39 citations

    1

    h-index

  5. arXiv (Cornell University)

    Repository · 1 publications · 127 citations

    1

    h-index

1–5