Fault Tolerance Verification
Fault Tolerance Verification is a formal method for verifying that a hybrid system correctly maintains specified functionality and safety properties in the presence of predefined faults or disturbances, through rigorous analysis of its dynamic and discrete behaviors.
25
Publications
542
Citations
62
Authors
34
Institutions
Publications per year
2017–2026
3
Parents
25
Formally Verifying Fault Tolerant System Designs
Cinzia Bernardeschi · The Computer Journal · 2000 · 30 citations
1–5 of 25
62
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Istituto di Scienza e Tecnologie dell'Informazione "Alessandro Faedo", Italy
2 publications · 26 citations
2
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2
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1
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1–5 of 62
34

Imperial College London
London, United Kingdom
2 h-index
4 publications
60 citations
SRI International
Menlo Park, United States
2 h-index
2 publications
125 citations

Centre National de la Recherche Scientifique
Paris, France
2 h-index
7 publications
137 citations

Laboratoire d'Analyse et d'Architecture des Systèmes
Toulouse, France
2 h-index
7 publications
137 citations
Menlo School
Atherton, United States
2 h-index
2 publications
125 citations
Istituto di Scienza e Tecnologie dell'Informazione "Alessandro Faedo"
Pisa, Italy
2 h-index
3 publications
40 citations
University of Florence
Florence, Italy
1 h-index
1 publications
12 citations
Verimag
Gières, France
1 h-index
2 publications
40 citations
1–8 of 34
2 publications · 44 citations
2
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MICPRO · 1 publications · 15 citations
1
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1 publications · 31 citations
1
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1 publications · 23 citations
1
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TSE · 1 publications · 100 citations
1
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1–5