Fault Tolerance Verification

Fault Tolerance Verification is a formal method for verifying that a hybrid system correctly maintains specified functionality and safety properties in the presence of predefined faults or disturbances, through rigorous analysis of its dynamic and discrete behaviors.

25

Publications

542

Citations

62

Authors

34

Institutions

Publications per year

2017–2026

3

Authors

62

  1. AL
    Alessio Lomuscio

    Imperial College London, United Kingdom

    2 publications · 30 citations

    2

    h-index

  2. CB
    Cinzia Bernardeschi

    University of Pisa, Italy

    2 publications · 42 citations

    2

    h-index

  3. SG
    Stefania Gnesi

    Istituto di Scienza e Tecnologie dell'Informazione "Alessandro Faedo", Italy

    2 publications · 26 citations

    2

    h-index

  4. JR
    John Rushby

    SRI International, United States

    2 publications · 125 citations

    2

    h-index

  5. CR
    C. Rodrı́guez

    Universidad de La Laguna, Spain

    1 publications · 20 citations

    1

    h-index

1–5 of 62

Venues

  1. IEEE Transactions on Computers

    2 publications · 44 citations

    2

    h-index

  2. Microprocessors and Microsystems

    MICPRO · 1 publications · 15 citations

    1

    h-index

  3. Distributed Computing

    1 publications · 31 citations

    1

    h-index

  4. 1

    h-index

  5. IEEE Transactions on Software Engineering

    TSE · 1 publications · 100 citations

    1

    h-index

1–5