Fault Tolerance Testing

Fault Tolerance Testing is a systematic validation methodology within Hardware-In-The-Loop Testing that evaluates the ability of a system to maintain correct operation in the presence of injected hardware or software faults, distinguishing it from other testing paradigms by its focus on resilience under operational failure conditions.

67

Publications

2.3K

Citations

170

Authors

67

Institutions

Publications per year

2017–2026

2

Authors

170

  1. MB
    M.A. Breuer

    University of Southern California, United States

    5 publications · 173 citations

    5

    h-index

  2. YC
    Yves Crouzet

    Laboratoire d'Analyse et d'Architecture des Systèmes, France

    5 publications · 336 citations

    5

    h-index

  3. JA
    Jean Arlat

    Laboratoire d'Analyse et d'Architecture des Systèmes, France

    4 publications · 254 citations

    4

    h-index

  4. JL
    J.-C. Laprie

    Laboratoire d'Analyse et d'Architecture des Systèmes, France

    3 publications · 239 citations

    3

    h-index

  5. VS
    Volkmar Sieh

    Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

    3 publications · 119 citations

    3

    h-index

1–5 of 170

Venues

  1. IEEE Transactions on Computers

    3 publications · 312 citations

    3

    h-index

  2. Information Processing Letters

    2 publications · 70 citations

    2

    h-index

  3. 2

    h-index

  4. 1

    h-index

  5. The American Journal of the Medical Sciences

    1 publications · 16 citations

    1

    h-index

1–5