False Path Constraints

False Path Constraints is a timing analysis directive in digital circuit design that identifies and excludes from timing verification paths that are logically or physically impossible to propagate signals, thereby preventing overly conservative timing closure.

14

Publications

592

Citations

33

Authors

16

Institutions

Publications per year

2017–2026

0

Authors

33

  1. GD
    Gary D. Hachtel

    University of Colorado Boulder, United States

    1 publications · 11 citations

    1

    h-index

  2. DK
    Dhiraj Kumar Goswami

    Mentor Technologies, United States

    1 publications · 15 citations

    1

    h-index

  3. KK
    Kurt Keutzer

    University of California, Berkeley, United States

    1 publications · 74 citations

    1

    h-index

  4. JS
    Jyuo-Min Shyu

    Industrial Technology Research Institute, Taiwan

    1 publications · 11 citations

    1

    h-index

  5. SH
    Sunik Heo

    1 publications · 11 citations

    1

    h-index

1–5 of 33