False Path Constraints
False Path Constraints is a timing analysis directive in digital circuit design that identifies and excludes from timing verification paths that are logically or physically impossible to propagate signals, thereby preventing overly conservative timing closure.
14
Publications
592
Citations
33
Authors
16
Institutions
Publications per year
2017–2026
0
Parents
14
Static timing analysis of dynamically sensitizable paths
S. Perremans, Luc Claesen, H. De Man · 1989 · 95 citations
On the false path problem in hard real-time programs
P. Altenbernd · 2002 · 93 citations
Timing analysis with known false sub graphs
K.P. Belkhale, Alexander J. Suess · 1995 · 21 citations
1–5 of 14
33
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1
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1
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1 publications · 11 citations
1
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1–5 of 33
16
IBM (United States)
Armonk, United States
2 h-index
2 publications
35 citations

National Taiwan University
Taipei, Taiwan
2 h-index
4 publications
52 citations
The University of Texas at Austin
Austin, United States
1 h-index
2 publications
30 citations
Massachusetts Institute of Technology
Cambridge, United States
1 h-index
3 publications
222 citations
The University of Texas at Dallas
Richardson, United States
1 h-index
1 publications
11 citations

Paderborn University
Paderborn, Germany
1 h-index
1 publications
93 citations
Texas A&M University
College Station, United States
1 h-index
1 publications
15 citations
Advanced Micro Devices (United States)
Sunnyvale, United States
1 h-index
1 publications
15 citations
1–8 of 16
2 publications · 26 citations
2
h-index
Conference · 1 publications · 11 citations
1
h-index
1 publications · 11 citations
1
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Conference · 1 publications · 14 citations
1
h-index
1 publications · 17 citations
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