Fall Delay

Fall Delay is a temporal metric in digital circuit timing analysis that quantifies the time interval required for a signal to transition from a high to a low logic state, distinguishing it from rise delay by specifically characterizing the falling edge transition behavior of a signal path.

21

Publications

575

Citations

65

Authors

37

Institutions

Publications per year

2017–2026

4

Variants

Falling Delay

Authors

65

  1. AN
    A. Nakagawa

    Toshiba (Japan), Japan

    1 publications · 16 citations

    1

    h-index

  2. BD
    Boris D. Andreev

    University of Rochester, United States

    1 publications · 19 citations

    1

    h-index

  3. JS
    Jan Stuyt

    Imec the Netherlands, Netherlands

    1 publications · 12 citations

    1

    h-index

  4. BC
    Barbara C. Tilley

    The University of Texas Health Science Center at Houston, United States

    1 publications · 80 citations

    1

    h-index

  5. BM
    Baleshwar Meena

    National Botanical Research Institute, India

    1 publications · 39 citations

    1

    h-index

1–5 of 65

Venues

  1. Journal of Physics D Applied Physics

    1 publications · 22 citations

    1

    h-index

  2. CIRP Annals

    1 publications · 54 citations

    1

    h-index

  3. 1

    h-index

  4. American Journal of Physics

    1 publications · 25 citations

    1

    h-index

  5. Military Medicine

    1 publications · 12 citations

    1

    h-index

1–5