Embedded System Verification
Embedded System Verification is a formal process belonging to the class of validation methodologies that specifically ensures an automotive embedded system's design and implementation conform to specified functional and non-functional requirements through rigorous, systematic, and often automated techniques.
299
Publications
9.6K
Citations
806
Authors
317
Institutions
Publications per year
2017–2026
43
Parents
299
Model-integrated development of embedded software
Gábor Karsai, János Sztipanovits, Ákos Lédeczi et al. · Proceedings of the IEEE · 2003 · 388 citations
Formal verification of hybrid systems
Rajeev Alur · 2011 · 210 citations
Thomas A. Henzinger, Pei-Hsin Ho, Howard Wong-Toi · 2002 · 205 citations
1–5 of 299
806
7
h-index
National University of Sciences and Technology, Pakistan
7 publications · 212 citations
7
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7
h-index
6
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6
h-index
1–5 of 806
317

Centre National de la Recherche Scientifique
Paris, France
10 h-index
23 publications
574 citations
University of California, Berkeley
Berkeley, United States
10 h-index
16 publications
2.5K citations
Cadence Design Systems (United States)
San Jose, United States
8 h-index
10 publications
674 citations
National University of Sciences and Technology
Islamabad, Pakistan
7 h-index
17 publications
571 citations

Vanderbilt University
Nashville, United States
7 h-index
13 publications
1.8K citations
Umm al-Qura University
Makkah al Mukarramah, Saudi Arabia
7 h-index
8 publications
262 citations

Linköping University
Linköping, Sweden
6 h-index
18 publications
714 citations
Mälardalen University
Västerås, Sweden
6 h-index
25 publications
468 citations
1–8 of 317
TECS · 6 publications · 120 citations
6
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ENTCS · 5 publications · 78 citations
5
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4 publications · 148 citations
4
h-index
4 publications · 69 citations
4
h-index
4 publications · 1K citations
4
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1–5