Concepedia

Dma Controller Architecture

DMA Controller Architecture is a hardware design framework that orchestrates direct memory access operations by enabling peripheral devices to transfer data to and from system memory independently of the central processing unit, distinguished by its dedicated control logic, address and data buses, and prioritization mechanisms for managing multiple DMA channels.

44

Publications

1.1K

Citations

163

Authors

46

Institutions

Publications per year

2017–2026

4

Variants

Dmac Architecture

Parents

Publications

44

The Balsa Asynchronous Circuit Synthesis System

Andrew Bardsley, D. Edwards · 2000 · 80 citations

, , +15

The APIC approach to high performance network interface design: protected DMA and other techniques

Zubin Dittia, Gurudatta M. Parulkar, J. R. Cox · 2002 · 78 citations · Full text

, , +17

Protected, user-level DMA for the SHRIMP network interface

Matthias A. Blumrich, Cezary Dubnicki, E.W. Felten et al. · 2002 · 72 citations

, , +17

PARDIS

Mahdi Nazm Bojnordi, Engin İpek · ACM SIGARCH Computer Architecture News · 2012 · 55 citations

, , +17

High Performance FPGA-Based DMA Interface for PCIe

Hossein Kavianipour, S. Muschter, C. Böhm · IEEE Transactions on Nuclear Science · 2014 · 50 citations

, , +17

1–5 of 44

Authors

163

  1. TY
    T. Yutaka

    Toshiba (Japan), Japan

    2 publications · 50 citations

    2

    h-index

  2. MO
    Masaaki Oka

    Yamaguchi University, Japan

    2 publications · 50 citations

    2

    h-index

  3. MS
    M. Suzuoki

    Toshiba (Japan), Japan

    2 publications · 50 citations

    2

    h-index

  4. AB
    Andrew Bardsley

    University of Manchester, United Kingdom

    2 publications · 97 citations

    2

    h-index

  5. LR
    Lorenzo Rota

    Karlsruhe Institute of Technology, Germany

    2 publications · 41 citations

    2

    h-index

1–5 of 163

Institutions

46

  1. University of Manchester

    Manchester, United Kingdom

    3 h-index

    5 publications

    128 citations

  2. University of Rochester

    Rochester, United States

    2 h-index

    4 publications

    152 citations

  3. Barcelona Supercomputing Center

    Barcelona, Spain

    2 h-index

    5 publications

    185 citations

  4. Karlsruhe Institute of Technology

    Karlsruhe, Germany

    2 h-index

    10 publications

    205 citations

  5. University of Washington

    Seattle, United States

    2 h-index

    5 publications

    84 citations

  6. Universitat Politècnica de Catalunya

    Barcelona, Spain

    2 h-index

    7 publications

    283 citations

  7. Harbin Institute of Technology

    Harbin, China

    1 h-index

    4 publications

    52 citations

  8. Politecnico di Milano

    Milan, Italy

    1 h-index

    4 publications

    44 citations

1–8 of 46

Venues

  1. IEEE Transactions on Nuclear Science

    4 publications · 102 citations

    4

    h-index

  2. ACM SIGARCH Computer Architecture News

    2 publications · 70 citations

    2

    h-index

  3. IEEE Micro

    1 publications · 49 citations

    1

    h-index

  4. Journal of Systems Architecture

    JSA · 1 publications · 17 citations

    1

    h-index

  5. Microelectronics Journal

    1 publications · 18 citations

    1

    h-index

1–5