Decoder-based Logic Design

Decoder-Based Logic Design is a combinational logic synthesis methodology that employs a decoder as the primary functional unit to generate minterms, enabling the implementation of arbitrary Boolean functions through sum-of-products expressions derived from the decoded inputs.

7

Publications

270

Citations

33

Authors

11

Institutions

Publications per year

2017–2026

4

Authors

33

  1. YC
    Yong Choi

    Sungkyunkwan University, South Korea

    1 publications · 37 citations

    1

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  2. RR
    Rajeev Ratna Vallabhuni

    Aeronautical Development Agency, India

    1 publications · 26 citations

    1

    h-index

  3. JK
    Ji‐Hoon Kang

    Jeju National University, South Korea

    1 publications · 37 citations

    1

    h-index

  4. PS
    Prabhpreet Singh

    Guru Nanak Dev University, India

    1 publications · 32 citations

    1

    h-index

  5. TC
    Tanay Chattopadhyay

    National Institute of Technology Agartala, India

    1 publications · 30 citations

    1

    h-index

1–5 of 33

Venues

  1. 1

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  2. 1

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  3. IEEE Embedded Systems Letters

    1 publications · 33 citations

    1

    h-index

  4. Sensors and Actuators B Chemical

    1 publications · 32 citations

    1

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  5. Microelectronics Journal

    1 publications · 30 citations

    1

    h-index

1–5