Data Hazard Handling is a processor microarchitecture technique that resolves dependencies between instructions caused by overlapping execution in pipelined processors by ensuring correct data availability before instruction completion.
5
Publications
79
Citations
23
Authors
12
Institutions
Publications per year
2017–2026
1
Parents
Publications
5
Operation tables for scheduling in the presence of incomplete bypassing
Aviral Shrivastava, Eugene Earlie, Nikil Dutt et al. · 2004 · 25 citations
A Comprehensive Analysis on Data Hazard for RISC32 5-Stage Pipeline Processor
Wei Pau Kiat, Kai‐Ming Mok, Wai‐Kong Lee et al. · 2017 · 12 citations
A high-performance double precision accumulator
Krishna K. Nagar, Jason D. Bakos · 2009 · 10 citations
1–5 of 5
Authors
23
- AS
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h-index
- SC
1
h-index
- MG
1
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- NJ
1
h-index
- AN
1
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1–5 of 23
Institutions
12
University of California, Irvine
Irvine, United States
1 h-index
3 publications
75 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
1 h-index
1 publications
12 citations
Intel (United States)
Santa Clara, United States
1 h-index
1 publications
25 citations
Irvine University
Cerritos, United States
1 h-index
1 publications
25 citations
University of Illinois Urbana-Champaign
Urbana, United States
1 h-index
2 publications
24 citations
STMicroelectronics (Czechia)
Prague, Czechia
1 h-index
1 publications
20 citations
University of South Carolina
Columbia, United States
1 h-index
2 publications
20 citations
University of Strathclyde
Glasgow, United Kingdom
1 h-index
1 publications
12 citations
1–8 of 12
Venues
- IEEE Transactions on Computers
1 publications · 12 citations
1
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