Cycle Stealing

Cycle Stealing is a direct memory access technique in which the DMA controller intermittently seizes control of the system bus to transfer data, thereby utilizing otherwise idle processor cycles without halting the CPU's execution.

26

Publications

809

Citations

40

Authors

22

Institutions

Publications per year

2017–2026

0

Authors

40

  1. AL
    Arnold L. Rosenberg

    University of Massachusetts Amherst, United States

    4 publications · 106 citations

    4

    h-index

  2. MH
    Mor Harchol‐Balter

    Carnegie Mellon University, United States

    3 publications · 88 citations

    3

    h-index

  3. TO
    Takayuki Osogami

    IBM Research - Tokyo, Japan

    3 publications · 88 citations

    3

    h-index

  4. TH
    Taiyi Huang

    National Tsing Hua University, Taiwan

    3 publications · 45 citations

    3

    h-index

  5. JK
    Jeffrey K. Hollingsworth

    University of Maryland, College Park, United States

    3 publications · 40 citations

    3

    h-index

1–5 of 40

Venues

  1. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 2 publications · 35 citations

    2

    h-index

  2. Journal of Parallel and Distributed Computing

    2 publications · 47 citations

    2

    h-index

  3. GCA

    2 publications · 25 citations

    2

    h-index

  4. Journal of Grid Computing

    1 publications · 12 citations

    1

    h-index

  5. Proceedings of the VLDB Endowment

    PVLDB · 1 publications · 261 citations

    1

    h-index

1–5