Cycle Stealing
Cycle Stealing is a direct memory access technique in which the DMA controller intermittently seizes control of the system bus to transfer data, thereby utilizing otherwise idle processor cycles without halting the CPU's execution.
26
Publications
809
Citations
40
Authors
22
Institutions
Publications per year
2017–2026
0
Parents
26
Robust Priority Assignment for Fixed Priority Real-Time Systems
2007 · 70 citations
Cycle stealing under immediate dispatch task assignment
Mor Harchol‐Balter, Takayuki Osogami, Alan Scheller‐Wolf et al. · 2003 · 29 citations
1–5 of 26
40
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University of Maryland, College Park, United States
3 publications · 40 citations
3
h-index
1–5 of 40
22
Carnegie Mellon University
Pittsburgh, United States
4 h-index
12 publications
327 citations

University of Massachusetts Amherst
Amherst Center, United States
3 h-index
3 publications
90 citations
University of Maryland, College Park
College Park, United States
3 h-index
5 publications
62 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
2 h-index
2 publications
41 citations
Arizona State University
Tempe, United States
2 h-index
2 publications
29 citations
Duke University
Durham, United States
2 h-index
5 publications
829 citations
IBM (United States)
Armonk, United States
2 h-index
6 publications
114 citations
University of Illinois Urbana-Champaign
Urbana, United States
2 h-index
5 publications
87 citations
1–8 of 22
TPDS · 2 publications · 35 citations
2
h-index
2 publications · 47 citations
2
h-index
2 publications · 25 citations
2
h-index
1 publications · 12 citations
1
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PVLDB · 1 publications · 261 citations
1
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