Current Mirror Matching Techniques is a methodological framework in analog integrated circuit design that enables precise replication of reference currents across multiple transistor branches by minimizing mismatches due to process, temperature, and layout variations through specialized device pairing, sizing, and layout strategies.
5
Publications
174
Citations
10
Authors
5
Institutions
Publications per year
2017–2026
0
Parents
Publications
5
1–5 of 5
Authors
10
- BL
2
h-index
- YB
1
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- TS
1
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- ML
1
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- TSTeresa Serrano‐Gotarredona
Instituto de Microelectrónica de Sevilla, Spain
1 publications · 49 citations
1
h-index
1–5 of 10
Institutions
5
Instituto de Microelectrónica de Sevilla
Seville, Spain
2 h-index
3 publications
148 citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
1 h-index
1 publications
35 citations
Iowa State University
Ames, United States
1 h-index
3 publications
75 citations
University of Oslo
Oslo, Norway
1 h-index
2 publications
30 citations
Centro Nacional de Microelectrónica
Barcelona, Spain
1 h-index
1 publications
50 citations
1–5 of 5
Venues
- IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing
1 publications · 50 citations
1
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- IEEE Journal of Solid-State Circuits
1 publications · 49 citations
1
h-index
- IEE Proceedings G Circuits Devices and Systems
1 publications · 35 citations
1
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- Analog Integrated Circuits and Signal Processing
1 publications · 39 citations
1–4