Constrained Random Verification is a verification methodology within the domain of hardware design testing that distinguishes itself by employing randomized test generation subject to user-defined constraints to achieve comprehensive coverage of design corner cases.
28
Publications
779
Citations
69
Authors
33
Institutions
Publications per year
2017–2026
8
Variants
Crv
Parents
Publications
28
Distance-Guided Hybrid Verification with GUIDO
Smitha Shyam, Valeria Bertacco · 2006 · 60 citations
Knowledge Compilation meets Uniform Sampling
Shubham Sharma, Rahul Gupta, Subhajit Roy et al. · EPiC series in computing · 2018 · 55 citations · Full text
1–5 of 28
Authors
69
- KS
5
h-index
- VB
3
h-index
- NK
3
h-index
- DJ
2
h-index
- MY
2
h-index
1–5 of 69
Institutions
33
University of California, Berkeley
Berkeley, United States
5 h-index
10 publications
404 citations
University of Michigan
Ann Arbor, United States
3 h-index
6 publications
272 citations
Amrita Vishwa Vidyapeetham
Coimbatore, India
2 h-index
4 publications
132 citations
University of Bremen
Bremen, Germany
2 h-index
5 publications
121 citations
Mentor Technologies
Tulsa, United States
2 h-index
3 publications
42 citations
University of California, Santa Barbara
Santa Barbara, United States
2 h-index
3 publications
77 citations
Siemens (Hungary)
Budapest, Hungary
2 h-index
3 publications
39 citations
Cadence Design Systems (United States)
San Jose, United States
2 h-index
2 publications
164 citations
1–8 of 33
Venues
- arXiv (Cornell University)
Repository · 3 publications · 52 citations
3
h-index
- Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
ICCAD · 2 publications · 102 citations
2
h-index
- Proceedings - IEEE Aerospace Conference
1 publications · 12 citations
1
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 publications · 15 citations
1
h-index
- Nuclear Engineering and Technology
1 publications · 11 citations
1
h-index
1–5