Concepedia

Clock Gating Semantics

Clock Gating Semantics is a timing semantics framework that formalizes the conditional propagation of clock signals in synchronous digital circuits by enabling or disabling clock distribution based on functional activity, thereby refining timing behavior to account for power-optimized circuit designs.

1

Publications

14

Citations

5

Authors

2

Institutions

Publications per year

2017–2026

0

Parents

Publications

1

1–1 of 1

Authors

5

  1. SS
    Sutirtha Sanyal

    Universitat Politècnica de Catalunya, Spain

    1 publications · 14 citations

    1

    h-index

  2. SR
    Sourav Roy

    National Institute of Technology Durgapur, India

    1 publications · 14 citations

    1

    h-index

  3. MV
    Mateo Valero

    Universitat Politècnica de Catalunya, Spain

    1 publications · 14 citations

    1

    h-index

  4. AC
    Adrián Cristal

    Universitat Politècnica de Catalunya, Spain

    1 publications · 14 citations

    1

    h-index

  5. OÜ
    Osman Ünsal

    Universitat Politècnica de Catalunya, Spain

    1 publications · 14 citations

    1

    h-index

1–5 of 5

Institutions

2

  1. Barcelona Supercomputing Center

    Barcelona, Spain

    1 h-index

    4 publications

    56 citations

  2. Universitat Politècnica de Catalunya

    Barcelona, Spain

    1 h-index

    4 publications

    56 citations

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