Concepedia

Clock Gating Efficiency

Clock Gating Efficiency is a metric that quantifies the effectiveness of clock gating in reducing dynamic power consumption by measuring the ratio of disabled clock cycles to total clock cycles in a given circuit or system.

2

Publications

66

Citations

15

Authors

4

Institutions

Publications per year

2017–2026

0

Parents

Publications

2

1–3 of 2

Authors

15

  1. AD
    Anand D. Darji

    Sardar Vallabhbhai National Institute of Technology Surat, India

    1 publications · 22 citations

    1

    h-index

  2. VZ
    Victor Zyuban

    IBM Research - Thomas J. Watson Research Center, United States

    1 publications · 44 citations

    1

    h-index

  3. JM
    Joel M. Tendler

    IBM (United States), United States

    1 publications · 44 citations

    1

    h-index

  4. SN
    S. N. Merchant

    Indian Institute of Technology Bombay, India

    1 publications · 22 citations

    1

    h-index

  5. AN
    A. N. Chandorkar

    Indian Institute of Technology Bombay, India

    1 publications · 22 citations

    1

    h-index

1–5 of 15

Institutions

4

  1. IBM Research - Thomas J. Watson Research Center

    Yorktown Heights, United States

    1 h-index

    5 publications

    220 citations

  2. IBM (United States)

    Armonk, United States

    1 h-index

    11 publications

    484 citations

  3. Indian Institute of Technology Bombay

    Mumbai, India

    1 h-index

    3 publications

    66 citations

  4. Sardar Vallabhbhai National Institute of Technology Surat

    Surat, India

    1 h-index

    1 publications

    22 citations

  5. Abdelmalek Essaâdi University

    Tétouan, Morocco

    1 publications

    16 citations

  6. Mohammed V University

    Rabat, Morocco

    1 publications

    16 citations

1–6 of 4

Venues

  1. EURASIP Journal on Image and Video Processing

    1 publications · 22 citations

    1

    h-index

1–1