Clock Gating Control Logic

Clock Gating Control Logic is a digital circuitry component that belongs to the class of power optimization techniques in synchronous digital systems, specifically characterized by its function of dynamically enabling or disabling the clock signal to sequential elements based on idle conditions to reduce dynamic power consumption.

3

Publications

265

Citations

14

Authors

5

Institutions

Publications per year

2017–2026

0

Authors

14

  1. LB
    Luca Benini

    University of Bologna, Italy

    2 publications · 238 citations

    2

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  2. GD
    Giovanni De Micheli

    École Polytechnique Fédérale de Lausanne, Switzerland

    2 publications · 238 citations

    2

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  3. YK
    Young‐Won Kim

    UES (United States), United States

    1 publications · 27 citations

    1

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  4. YP
    Yoon-Suk Park

    Samsung (South Korea), South Korea

    1 publications · 27 citations

    1

    h-index

  5. PH
    Paul H. Siegel

    University of California San Diego, United States

    1 publications · 170 citations

    1

    h-index

1–5 of 14

Venues

  1. IEEE Design & Test of Computers

    1 publications · 170 citations

    1

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  2. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 1 publications · 68 citations

    1

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  3. 1

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