Clock Gating Control Logic
Clock Gating Control Logic is a digital circuitry component that belongs to the class of power optimization techniques in synchronous digital systems, specifically characterized by its function of dynamically enabling or disabling the clock signal to sequential elements based on idle conditions to reduce dynamic power consumption.
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Publications
265
Citations
14
Authors
5
Institutions
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2017–2026
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École Polytechnique Fédérale de Lausanne, Switzerland
2 publications · 238 citations
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Stanford University
Stanford, United States
2 h-index
4 publications
476 citations
Politecnico di Torino
Turin, Italy
1 h-index
3 publications
204 citations
Sungkyunkwan University
Seoul, South Korea
1 h-index
6 publications
162 citations
Hewlett-Packard (Japan)
Tokyo, Japan
1 h-index
1 publications
170 citations
Samsung (South Korea)
Seoul, South Korea
1 h-index
2 publications
54 citations
1–5 of 5
1 publications · 170 citations
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TODAES · 1 publications · 68 citations
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1 publications · 27 citations
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