Cache Invalidations is a coherence protocol mechanism in shared-memory multiprocessing systems that belongs to the class of cache management techniques, specifically distinguished by its function of marking cached data as stale or unusable upon updates to the corresponding memory location in another processor’s cache.
79
Publications
3.3K
Citations
172
Authors
68
Institutions
Publications per year
2017–2026
7
Variants
Cache Invalidation
Publications
79
1–5 of 79
Authors
172
- JD
5
h-index
- HC
4
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- MD
4
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- SJ
3
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- AR
3
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1–5 of 172
Institutions
68
Georgia Institute of Technology
Atlanta, United States
6 h-index
18 publications
441 citations
University of Illinois Urbana-Champaign
Urbana, United States
6 h-index
12 publications
552 citations
University of Southern California
Los Angeles, United States
5 h-index
15 publications
847 citations
University of Washington
Seattle, United States
5 h-index
5 publications
284 citations
University of Rochester
Rochester, United States
5 h-index
7 publications
355 citations
Universitat Politècnica de València
Valencia, Spain
4 h-index
15 publications
946 citations
Engineering Systems (United States)
Omaha, United States
4 h-index
10 publications
453 citations
University of California, Berkeley
Berkeley, United States
3 h-index
3 publications
190 citations
1–8 of 68
Venues
- ACM SIGARCH Computer Architecture News
8 publications · 342 citations
8
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- IEEE Transactions on Parallel and Distributed Systems
TPDS · 4 publications · 193 citations
4
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- IEEE Transactions on Computers
4 publications · 261 citations
4
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- Proceedings of the International Conference on Parallel Processing
Conference · 3 publications · 49 citations
3
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- Computer Networks
2 publications · 94 citations
2
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1–5