Bit-Level Modeling is a hardware modeling approach that represents digital systems by explicitly defining the behavior and structure of individual binary digits, distinguishing it from higher-level abstractions by focusing on signal-level operations and bitwise precision.
133
Publications
9.2K
Citations
366
Authors
173
Institutions
Publications per year
2017–2026
35
Publications
133
<i>adegenet 1.3-1</i> : new tools for the analysis of genome-wide SNP data
Thibaut Jombart, Ismaïl Ahmed · Bioinformatics · 2011 · 3.3K citations · Full text
Efficient implementation of property directed reachability
Niklas Eén, Alan Mishchenko, Robert K. Brayton · 2011 · 276 citations
1–5 of 133
Authors
366
- DS
3
h-index
- GP
3
h-index
- WK
3
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- MC
3
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- RK
3
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1–5 of 366
Institutions
173
Centre National de la Recherche Scientifique
Paris, France
5 h-index
9 publications
218 citations
University of Verona
Verona, Italy
4 h-index
9 publications
148 citations
University of California, Berkeley
Berkeley, United States
4 h-index
9 publications
968 citations
Carnegie Mellon University
Pittsburgh, United States
4 h-index
7 publications
317 citations
University of Kaiserslautern
Kaiserslautern, Germany
3 h-index
8 publications
173 citations
University of Tübingen
Tübingen, Germany
3 h-index
3 publications
38 citations
Dalian University of Technology
Dalian, China
3 h-index
4 publications
385 citations
Dalian University
Dalian, China
3 h-index
4 publications
385 citations
1–8 of 173
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
4 publications · 162 citations
4
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- IEEE Access
4 publications · 65 citations
4
h-index
- Multimedia Tools and Applications
3 publications · 141 citations
3
h-index
- IEEE Transactions on Instrumentation and Measurement
3 publications · 67 citations
3
h-index
- IEEE Transactions on Circuits and Systems
2 publications · 206 citations
2
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1–5