Analog Placement Optimization
Analog Placement Optimization is a design methodology within analog integrated circuit synthesis that systematically determines the optimal physical arrangement of circuit components to minimize parasitic effects, enhance matching, and improve overall performance metrics under geometric and routing constraints.
54
Publications
1.9K
Citations
131
Authors
42
Institutions
Publications per year
2017–2026
9
Parents
54
1–5 of 54
131
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Chinese University of Hong Kong, Hong Kong SAR China
4 publications · 123 citations
4
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4
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1–5 of 131
42

National Taiwan University
Taipei, Taiwan
7 h-index
18 publications
692 citations
Instituto de Telecomunicações
Lisbon, Portugal
5 h-index
12 publications
284 citations
Chinese University of Hong Kong
Hong Kong, Hong Kong
4 h-index
10 publications
317 citations
University of Lisbon
Lisbon, Portugal
3 h-index
2 publications
30 citations
National Central University
Taoyuan City, Taiwan
3 h-index
11 publications
263 citations
Centro Nacional de Microelectrónica
Barcelona, Spain
3 h-index
9 publications
548 citations
Tsinghua University
Beijing, China
3 h-index
11 publications
332 citations
Memorial University of Newfoundland
St. John's, Canada
3 h-index
4 publications
93 citations
1–8 of 42
5 publications · 308 citations
5
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2 publications · 38 citations
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Conference · 2 publications · 99 citations
2
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2 publications · 69 citations
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2 publications · 24 citations
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