Analog Placement Optimization

Analog Placement Optimization is a design methodology within analog integrated circuit synthesis that systematically determines the optimal physical arrangement of circuit components to minimize parasitic effects, enhance matching, and improve overall performance metrics under geometric and routing constraints.

54

Publications

1.9K

Citations

131

Authors

42

Institutions

Publications per year

2017–2026

9

Authors

131

  1. NH
    Nuno Horta

    Instituto de Telecomunicações, Portugal

    3 publications · 76 citations

    5

    h-index

  2. RM
    Ricardo Martins

    Instituto de Telecomunicações, Portugal

    3 publications · 76 citations

    5

    h-index

  3. YC
    Yao‐Wen Chang

    National Taiwan University, Taiwan

    5 publications · 221 citations

    5

    h-index

  4. EF
    Evangeline F. Y. Young

    Chinese University of Hong Kong, Hong Kong SAR China

    4 publications · 123 citations

    4

    h-index

  5. HO
    Hung-Chih Ou

    National Taiwan University, Taiwan

    4 publications · 114 citations

    4

    h-index

1–5 of 131

Venues

  1. 5

    h-index

  2. Integration

    2 publications · 38 citations

    2

    h-index

  3. International Conference on Computer Aided Design

    Conference · 2 publications · 99 citations

    2

    h-index

  4. 2

    h-index

  5. 2

    h-index

1–5