Concepedia

Allocation For Instruction-level Parallelism

Allocation for Instruction-Level Parallelism is a register allocation technique that optimizes the assignment of variables to processor registers by explicitly enabling parallel execution of instructions within a basic block through the careful management of data dependencies and resource conflicts.

13

Publications

503

Citations

40

Authors

12

Institutions

Publications per year

2017–2026

0

Parents

Publications

13

Virtual-physical registers

Antonio González, J. M. Gonzalez Castro, Mateo Valero · 2002 · 123 citations · Full text

, , +14

Application scheduling and processor allocation in multiprogrammed parallel processing systems

K. C. Sevcik · Performance Evaluation · 1994 · 117 citations

, , +16

A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

Yu Zhang, Dongdong Chen, Younhee Choi et al. · Microprocessors and Microsystems · 2010 · 61 citations

, , +14

Global predicate analysis and its application to register allocation

David M. Gillies, Dz-ching Roy Ju, Richard Johnson et al. · 1996 · 40 citations

, , +14

Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers

David A. Berson, Rajiv Gupta, Mary Lou Soffa · 1994 · 29 citations

, , +12

1–5 of 13

Authors

40

  1. AS
    André Seznec

    Institut de Recherche en Informatique et Systèmes Aléatoires, France

    2 publications · 38 citations

    2

    h-index

  2. DB
    David Black-Shaffer

    Uppsala University, Sweden

    2 publications · 38 citations

    2

    h-index

  3. EH
    Erik Hägersten

    Uppsala University, Sweden

    2 publications · 38 citations

    2

    h-index

  4. TE
    Trevor E. Carlson

    Uppsala University, Sweden

    2 publications · 38 citations

    2

    h-index

  5. MS
    Michael Schlansker

    Hewlett-Packard (United States), United States

    2 publications · 58 citations

    2

    h-index

1–5 of 40

Institutions

12

  1. Universitat Politècnica de Catalunya

    Barcelona, Spain

    2 h-index

    5 publications

    421 citations

  2. Hewlett-Packard (United States)

    Palo Alto, United States

    2 h-index

    8 publications

    232 citations

  3. Institut national de recherche en sciences et technologies du numérique

    Le Chesnay-Rocquencourt, France

    1 h-index

    3 publications

    75 citations

  4. Universidad de Zaragoza

    Zaragoza, Spain

    1 h-index

    2 publications

    52 citations

  5. University of Saskatchewan

    Saskatoon, Canada

    1 h-index

    5 publications

    305 citations

  6. KTH Royal Institute of Technology

    Stockholm, Sweden

    1 h-index

    2 publications

    28 citations

  7. Uppsala University

    Uppsala, Sweden

    1 h-index

    4 publications

    100 citations

  8. Technische Universität Dresden

    Dresden, Germany

    1 h-index

    2 publications

    20 citations

1–8 of 12

Venues

  1. Microprocessors and Microsystems

    MICPRO · 2 publications · 71 citations

    2

    h-index

  2. Performance Evaluation

    1 publications · 117 citations

    1

    h-index

  3. IEEE Transactions on Computers

    1 publications · 26 citations

    1

    h-index

  4. HAL (Le Centre pour la Communication Scientifique Directe)

    Repository · 1 publications · 13 citations

    1

    h-index

1–4