1c:I[204933,["/_next/static/chunks/bb923814e1f4d2e9.js","/_next/static/chunks/dd3ee9f5b7716ca6.js","/_next/static/chunks/4204a0ae82542ca8.js","/_next/static/chunks/1270dead247da766.js","/_next/static/chunks/6e1aa89a642f40be.js","/_next/static/chunks/b3eb9795ffa7b0d3.js","/_next/static/chunks/8ffd0b71567920d8.js","/_next/static/chunks/67ea6dfd21f16c5f.js","/_next/static/chunks/24eb4379f68013fd.js","/_next/static/chunks/b8cd775ffdf935bd.js","/_next/static/chunks/983103cd9eb7b428.js","/_next/static/chunks/263f2cdcb9aa2341.js","/_next/static/chunks/294b9525248c8e5f.js"],"default"] 1d:T50d,This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM). Emerging NVM cell characteristics are summarized, and device-level engineering trends are discussed. Emerging NVM array architectures are introduced, including the one-transistor-one-resistor (1T1R) array and the cross-point array with selectors. Design challenges such as scaling the write current and minimizing the sneak path current in cross-point array are analyzed. Recent progress on megabit-to gigabit-level prototype chip demonstrations is summarized. Finally, the prospective applications of emerging NVM are discussed, ranging from the last-level cache to the storage-class memory in the memory hierarchy. Topics of three-dimensional (3D) integration and radiation-hard NVM are discussed. Novel applications beyond the conventional memory applications are also surveyed, including physical unclonable function for hardware security, reconfigurable routing switch for field-programmable gate array (FPGA), logic-in-memory and nonvolatile cache/register/flip-flop for nonvolatile processor, and synaptic device for neuro-inspired computing.1e:T47e,Processing-in-memory (PIM) provides high bandwidth, massive parallelism, and high energy efficiency by implementing computations in main memory, therefore eliminating the overhead of data movement between CPU and memory. While most of the recent work focused on PIM in DRAM memory with 3D die-stacking technology, we propose to leverage the unique features of emerging non-volatile memory (NVM), such as resistance-based storage and current sensing, to enable efficient PIM design in NVM. We propose Pinatubo1, a Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations. Instead of integrating complex logic inside the cost-sensitive memory, Pinatubo redesigns the read circuitry so that it can compute the bitwise logic of two or more memory rows very efficiently, and support one-step multi-row operations. The experimental results on data intensive graph processing and database applications show that Pinatubo achieves a ~500× speedup, ~28000× energy saving on bitwise operations, and 1.12× overall speedup, 1.11× overall energy saving over the conventional processor.1f:T79e,

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