Hideharu Amano

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano et al. · 2008 · 131 citations

Hardware Security, Fault-tolerant Network, Engineering +15

A case for random shortcut topologies for HPC interconnects

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano et al. · ACM SIGARCH Computer Architecture News · 2012 · 95 citations

Cluster Computing, Engineering, High Performance Computer Network +17

Prediction router: Yet another low latency on-chip router architecture

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano et al. · 2009 · 91 citations

Engineering, Computer Architecture, Network Analysis +16

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi et al. · 2010 · 71 citations

Hardware Security, Electrical Engineering, Power-aware Computing +15

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano · Proceedings of the International Conference on Parallel Processing · 2007 · 61 citations

Engineering, Routing Algorithm, Computer Architecture +19