Amit Goel

Statistical waveform and current source based standard cell models for accurate timing analysis

Amit Goel, Sarma Vrudhula · 2008 · 28 citations

Statistical Waveform, Engineering, Vlsi Design +21

Deciding array formulas with frugal axiom instantiation

Amit Goel, Sava Krstić, Alexander Fuchs · 2008 · 27 citations

Array Axioms, Engineering, Lazy Axiom Instantiation +21

A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations

Sarvesh Bhardwaj, Sarma Vrudhula, Amit Goel · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008 · 22 citations

Engineering, Vlsi Design, Signal Arrival Times +18

Current source based standard cell model for accurate signal integrity and timing analysis

Amit Goel, Sarma Vrudhula · 2008 · 21 citations

Engineering, Vlsi Design, Stage Delay +20

A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations

Amit Goel, Sarma Vrudhula, Feroze Taraporevala et al. · 2008 · 10 citations

Engineering, Vlsi Design, Computer Architecture +28