Terng-Yin Hsu

An all-digital phase-locked loop (ADPLL)-based clock recovery circuit

Terng-Yin Hsu, Bai-Jue Shieh, Chen‐Yi Lee · IEEE Journal of Solid-State Circuits · 1999 · 60 citations

Fast Acquisition, Engineering, Clock Recovery +8

Design and analysis of a portable high-speed clock generator

Terng-Yin Hsu, Chung‐Cheng Wang, Chen‐Yi Lee · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2001 · 41 citations

Low-power Electronics, Fast Acquisition, Electrical Engineering +12

A Novel Technique for I/Q Imbalance and CFO Compensation in OFDM Systems

Jui-Yuan Yu, Ming-Fu Sun, Terng-Yin Hsu et al. · 2005 · 24 citations

Multi-carrier Communication, I/q Imbalance, Ofdm System +7

Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback

Jung-Chin Lai, Terng-Yin Hsu · IEEE Transactions on Industrial Electronics · 2017 · 24 citations

Time-residue Feedback Scheme, Electrical Engineering, Energy Harvesting +14

Design and Implementation of a Multi-Threading Architecture for Downlink Process in Software- Defined Physical Layer Over Long-Term Evolution Networks

Sendren Sheng‐Dong Xu, Terng-Yin Hsu, Yu‐Cheng Chen et al. · IEEE Transactions on Vehicular Technology · 2024 · 20 citations