Maxime Nassar

BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation

Maxime Nassar, Shivam Bhasin, Jean‐Luc Danger et al. · Design, Automation, and Test in Europe · 2010 · 62 citations

Cryptographic Primitive, Early Evaluation, Vlsi Design +21

BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation

Maxime Nassar, Shivam Bhasin, Jean‐Luc Danger et al. · 2010 · 56 citations

Cryptographic Primitive, Early Evaluation, Vlsi Design +21

Overview of Dual rail with Precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors

Jean‐Luc Danger, Sylvain Guilley, Shivam Bhasin et al. · 2009 · 46 citations

Cryptographic Primitive, Engineering, Information Security +21

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints

Laurent Sauvage, Sylvain Guilley, Jean‐Luc Danger et al. · 2009 · 35 citations · Full text

Route Constraints, Engineering, Information Security +17

Place-and-route impact on the security of DPL designs in FPGAs

Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage et al. · 2008 · 27 citations

Cryptographic Primitive, Engineering, Information Security +17