Shourya Gupta

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Shourya Gupta, Kirti Gupta, Benton H. Calhoun et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2018 · 81 citations

Non-volatile Memory, Engineering, Vlsi Design +19

Comparison of conventional and new flipped voltage structures with increased input/output signal swing and current sourcing/sinking capabilities

J. Ramírez‐Angulo, Shourya Gupta, R.G. Carvajal et al. · 2005 · 65 citations

Electrical Engineering, Engineering, Circuit System +7

A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist

Shourya Gupta, Kirti Gupta, Neeta Pandey · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2017 · 62 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +12

A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability

Prakhar Sharma, Shourya Gupta, Kirti Gupta et al. · Microelectronics Journal · 2020 · 47 citations

Pentavariate <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{min}}$ </tex-math> </inline-formula> Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read

Shourya Gupta, Kirti Gupta, Neeta Pandey · IEEE Transactions on Circuits and Systems I Regular Papers · 2018 · 38 citations

Engineering, Vlsi Design, Memory Design +19