Debashis Mandal

Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time

Debashis Mandal, Chirag Desai, Bertan Bakkaloğlu et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2018 · 69 citations

Engineering, Computer Engineering, Low-power Design +16

A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error

Ming Sun, Zhe Yang, Kishan Joshi et al. · IEEE Journal of Solid-State Circuits · 2017 · 44 citations

Engineering, Electrical Engineering, Analog Electronics +14

A 100-mA, 99.11% Current Efficiency, 2-mV_pp Ripple Digitally Controlled LDO With Active Ripple Suppression

Michael Cheah, Debashis Mandal, Bertan Bakkaloğlu et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2016 · 43 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time

Chirag Desai, Debashis Mandal, Bertan Bakkaloğlu et al. · IEEE Solid-State Circuits Letters · 2018 · 42 citations

Engineering, Computer Engineering, Analog Electronics +16

Online Built-In Self-Test of High Switching Frequency DC–DC Converters Using Model Reference Based System Identification Techniques

Navankur Beohar, Venkata N.K Malladi, Debashis Mandal et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2017 · 36 citations

Engineering, Computer Engineering, Electrical Engineering +17