Hideo Ito

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit

Y. Sasaki, Kazuteru Namba, Hideo Ito · Proceedings · 2006 · 68 citations

Hardware Security, Electrical Engineering, Engineering +11

Defect and fault tolerance FPGAs by shifting the configuration data

Abderrahim Doumar, Shun’ichi Kaneko, Hideo Ito · 2003 · 63 citations

Hardware Security, Hardware Architecture, Reliability Engineering +15

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

Abderrahim Doumar, Hideo Ito · International Conference on Computer Design · 2003 · 51 citations

Engineering, Vlsi Design, Mem Testing +17

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

Abderrahim Doumar, Hideo Ito · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003 · 44 citations

Engineering, Vlsi Design, Mem Testing +17

Testing the logic cells and interconnect resources for FPGAs

Abderrahim Doumar, Hideo Ito · 2003 · 35 citations

Hardware Security, Electrical Engineering, New Design +15