Young-Hun Seo

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$m CMOS

Seon‐Kyoo Lee, Young-Hun Seo, Hong‐June Park et al. · IEEE Journal of Solid-State Circuits · 2010 · 147 citations

Engineering, All-digital Pll, Data Converter +11

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$m CMOS

Young-Hun Seo, Junseok Kim, Hong-June Park et al. · IEEE Journal of Solid-State Circuits · 2011 · 74 citations

Engineering, Vlsi Design, Ps Resolution 8B +10

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS

Junseok Kim, Young-Hun Seo, Yunjae Suh et al. · IEEE Journal of Solid-State Circuits · 2012 · 57 citations

Engineering, Vlsi Design, Calibration +14

A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate

Seon‐Kyoo Lee, Young-Sang Kim, Hyunsoo Ha et al. · 2009 · 54 citations

Network Timing, Cdr Circuit, Engineering +12

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping $\Delta\Sigma$ TDC

Dong‐Woo Jee, Young-Hun Seo, Hong-June Park et al. · IEEE Journal of Solid-State Circuits · 2012 · 42 citations

σ Modulator, Data Converter, Mixed-signal Integrated Circuit +6