Concepedia

Veeresh Taranalli

VT

Statistics

Publications

5

Citations

126

H-Index

5

Active since

2015

Affiliations

University of California San Diego(Current)

Toshiba (Japan)

Veeresh Taranalli is an author at University of California San Diego specializing in engineering, polar codes, and iterative decoding.

Top concepts

EngineeringPolar CodesComputer ScienceIterative DecodingCoding TheorySignal ProcessingComputer EngineeringComputational ComplexityMemoryMagnetism

Publications per year

2015–2017

5

Publications

5

Error analysis and inter-cell interference mitigation in multi-level cell flash memories

Veeresh Taranalli, Hironori Uchikawa, Paul H. Siegel · 2015 · 47 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +14

Channel Models for Multi-Level Cell Flash Memories Based on Empirical Error Analysis

Veeresh Taranalli, Hironori Uchikawa, Paul H. Siegel · IEEE Transactions on Communications · 2016 · 37 citations · Full text

Permuted successive cancellation decoding for polar codes

Sarit Buzaglo, Arman Fazeli, Paul H. Siegel et al. · 2017 · 19 citations

Engineering, Polar Design, Polar Codes +11

On Efficient Decoding of Polar Codes with Large Kernels

Sarit Buzaglo, Arman Fazeli, Paul H. Siegel et al. · 2017 · 12 citations

Engineering, Polar Design, Polar Codes +11

Polar codes for magnetic recording channels

A. K. Bhatia, Veeresh Taranalli, Paul H. Siegel et al. · 2015 · 11 citations

Magnetism, Engineering, Magnetic Data Storage +10

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