William L. Lynch

The effect of page allocation on caches

William L. Lynch, Brian K. Bray, Michael Flynn · ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter · 1992 · 30 citations · Full text

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency

R. Heald, Keun Wook Shin, V. Reddy et al. · IEEE Journal of Solid-State Circuits · 1998 · 26 citations

Hardware Security, Memory Architecture, Engineering +14

Smith-Waterman implementation on a FSB-FPGA module using the Intel Accelerator Abstraction Layer

Jeff Allred, Jack Coyne, William L. Lynch et al. · 2009 · 24 citations

Engineering, Advanced Computing, Hardware Algorithm +19

Low load latency through sum-addressed memory (SAM)

William L. Lynch, G. Lauterbach, Joseph I. Chamdani · 1998 · 17 citations

Engineering, Low Load Latency, Cache-hit Latency +10

Low-Latency FPGA Based Financial Data Feed Handler

Robin Pottathuparambil, Jack Coyne, Jeffrey Allred et al. · 2011 · 17 citations

Hardware Architecture, Engineering, Hardware Acceleration +13