António Canelas

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Nuno Lourenço, Ricardo Martins, António Canelas et al. · Integration · 2016 · 64 citations

In-loop Layout Generation, Electrical Engineering, Physical Design (Electronics) +6

On the Exploration of Promising Analog IC Designs via Artificial Neural Networks

Nuno Lourenço, João P. S. Rosa, Ricardo Martins et al. · 2018 · 51 citations

Electrical Engineering, Physical Design (Electronics), Engineering +14

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

Ricardo Martins, Nuno Lourenço, Fábio Passos et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2018 · 40 citations · Full text

Engineering, Electronic Design, Layout Design Steps +17

Floorplan-aware analog IC sizing and optimization based on topological constraints

Nuno Lourenço, António Canelas, Ricardo Póvoa et al. · Integration · 2014 · 34 citations

3D Ic Architecture, Physical Design (Electronics), Engineering +6

FUZYE: A Fuzzy ${c}$ -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms

António Canelas, Ricardo Póvoa, Ricardo Martins et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2018 · 34 citations

Differential Evolution, Fuzzy Logic, Engineering +13