Yu-Wen Tsay

Combining technology mapping and placement for delay-optimization in FPGA designs

Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang et al. · International Conference on Computer Aided Design · 1993 · 26 citations

Engineering, Routing Delay, Technology Mapping +16

Integrating logic retiming and register placement

Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay et al. · 1998 · 23 citations

Applied Logic, Engineering, Software Systems +21

A row-based cell placement method that utilizes circuit structural properties

Yu-Wen Tsay, Youn-Long Lin · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1995 · 12 citations

Engineering, Vlsi Design, Electronic Design Automation +17

Combining technology mapping and placement for delay-optimization in FPGA designs

C.-S. Chen, Yu-Wen Tsay, TingTing Hwang et al. · Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) · 2002 · 12 citations

Engineering, Routing Delay, Technology Mapping +18

Preserving HDL synthesis hierarchy for cell placement

Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu et al. · 1997 · 11 citations

Logic Synthesis, Computational Science, Engineering +14