Andrés Viveros-Wacher

System Margining Surrogate-Based Optimization in Post-Silicon Validation

Francisco E. Rangel-Patiño, José L. Chávez‐Hurtado, Andrés Viveros-Wacher et al. · IEEE Transactions on Microwave Theory and Techniques · 2017 · 25 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +15

Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks

Francisco E. Rangel-Patiño, José E. Rayas‐Sánchez, Andrés Viveros-Wacher et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2018 · 21 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +10

Analog Gross Fault Identification in RF Circuits Using Neural Models and Constrained Parameter Extraction

Andrés Viveros-Wacher, José E. Rayas‐Sánchez, Zabdiel Brito‐Brito · IEEE Transactions on Microwave Theory and Techniques · 2019 · 18 citations · Full text

Engineering, Electrical Engineering, Analog Electronics +16

A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation

Francisco E. Rangel-Patiño, Andrés Viveros-Wacher, José E. Rayas‐Sánchez et al. · 2016 · 16 citations · Full text

Engineering, Electrical Engineering, Systems Engineering +15

Analog Fault Identification in RF Circuits using Artificial Neural Networks and Constrained Parameter Extraction

Andrés Viveros-Wacher, José E. Rayas‐Sánchez · 2018 · 16 citations · Full text

Engineering, Electrical Engineering, Analog Electronics +16