For the first time, device design guidelines for a 3-nm node complementary field-effect transistor (CFET), which vertically stacks n-type and p-type nanosheet MOSFETs with a shared gate, are investigated using calibrated 3-D technology computer-aided design (TCAD). Here, the optimal device dimensions of the CFETs for better inverter performance and thermal characteristics are studied. The electrothermal performance are investigated for various vertical dimension parameters of CFET, such as the number of stacked channels, vertical distance between nanosheet channels (D _nsh ), distance of n/pMOS separation (D _n/p ), and channel thicknesses (T _nsh ). The results show that, unlike conventional CMOS, the reduction of D _nsh and D _n/p of CFET can effectively improve inverter performance without severe thermal degradation, although other dimensional parameters trigger a severe trade-off between different electrothermal parameters. The reduction of D _nsh and D _n/p decreases C _eff with a lower metal via the height and gate fringing effect. However, the reduction in D _nsh and D _n/p does not change R _eff ; therefore, both the operation frequency (

$f$

) and power-product delay (PDP) can be improved. In the case of thermal characteristics, the reduction of D _nsh and D _n/p slightly increases both T _max and R _th because of thermal coupling but is negligible. Therefore, the reduction of D _nsh and D _n/p will be a key technique for the development of sub-3-nm CFET.

Dong-Won Jang

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